module toy_cpu(
  input clk,
  input rst,

  input ex_intr,
  input mtip_clear,
  input msip_i,
  input msip_valid_i,
  output msip_o,
  input tim_int_req,
  //icache interface
  output icache_ren,
  output [63:0] icache_raddr,
  input icache_rbusy,
  input [31:0] icache_rdata, 
  input icache_rdata_valid,
  output icache_invalid,

  //dcache interface
  output dcache_ren,
  output [63:0] dcache_raddr,
  output [3:0] dcache_rsize,
  input dcache_rbusy,
  input [63:0] dcache_rdata, 
  input dcache_rdata_valid,

  input  dcache_wbusy,
  output dcache_wen,
  output [63:0] dcache_waddr,
  output [63:0] dcache_wdata, 
  output [3:0] dcache_wsize

);
  wire fetch_enable,decode_enable,execute_enable,memory_enable,writeback_enable;
  wire fetch_ready,decode_ready,execute_ready,memory_ready,writeback_ready;
  wire fetch_flush,decode_flush,execute_flush,memory_flush,writeback_flush;
  wire writeback_busy,memory_busy,execute_busy,decode_busy,fetch_busy;
  wire mul_ready,div_ready;
  assign fetch_busy = icache_rbusy;
  assign decode_busy = 1'b0;
  assign execute_busy = ~(mul_ready&div_ready);
  assign memory_busy = dcache_rbusy|dcache_wbusy;
  assign writeback_busy = 1'b0;
  wire [63:0] next_pc,pc;
  wire next_pc_valid;
  PC inst_PC
  (
    .clk             (clk),
    .rst             (rst),
    .next_pc_i       (next_pc),
    .next_pc_valid_i (next_pc_valid),
    .pc_o            (pc)
  );
  wire fetch_branch_valid_i,fetch_branch_valid_o,fetch_rdata_valid_i,fetch_ren_o;
  wire [31:0] fetch_rdata_i,fetch_inst_o;
  wire [63:0] fetch_raddr_o,fetch_pc_o,fetch_pc_i,fetch_next_pc_o,fetch_branch_pc_i;
  wire fetch_valid_o,fetch_branch_valid_o;



  assign fetch_rdata_i = icache_rdata;
  assign icache_raddr = fetch_raddr_o;
  assign icache_ren = fetch_ren_o;
  assign fetch_rdata_valid_i = icache_rdata_valid;

  assign fetch_pc_i = pc;
  assign next_pc_valid = fetch_branch_valid_o|fetch_enable;
  assign next_pc = fetch_next_pc_o;

  Fetch inst_Fetch
  (
    .enable         (fetch_enable),
    .flush          (fetch_flush),
    .ready          (fetch_ready),
    .pc_i           (fetch_pc_i),
    .next_pc_o      (fetch_next_pc_o),
    .branch_valid_o (fetch_branch_valid_o),
    .rdata_valid    (fetch_rdata_valid_i),
    .rdata          (fetch_rdata_i),
    .raddr          (fetch_raddr_o),
    .ren            (fetch_ren_o),
    .branch_pc      (fetch_branch_pc_i),
    .branch_valid_i (fetch_branch_valid_i),
    .pc_o           (fetch_pc_o),
    .inst_o         (fetch_inst_o),
    .valid_o        (fetch_valid_o)
  );
  wire decode_inst_valid_i;
  wire [31:0] decode_inst_i;
  wire [63:0] decode_pc_i;
  IF_reg inst_IF_reg
  (
    .clk       (clk),
    .rst       (rst),
    .flush     (fetch_flush),
    .enable    (fetch_enable),
    .ready     (decode_ready),
    .valid_i   (fetch_valid_o),
    .inst_pc_i (fetch_pc_o),
    .inst_i    (fetch_inst_o),
    .inst_pc_o (decode_pc_i),
    .inst_o    (decode_inst_i),
    .valid_o   (decode_inst_valid_i)
  );

  wire [63:0] decode_wdata_i;
  wire [4:0] decode_waddr_i;
  wire decode_wen_i;
  

  wire [31:0] decode_inst_o;
  wire decode_op_valid_o;
  wire [63:0] decode_pc_o,decode_src1_o,decode_src2_o,decode_imm_o;
  wire [4:0] decode_dest_o,decode_rs1_o,decode_rs2_o;
  wire [6:0] decode_arithmetic_op_o;
  wire [21:0] decode_logic_op_o;
  wire [7:0] decode_branch_op_o;
  wire [7:0] decode_load_op_o;
  wire [3:0] decode_store_op_o;
  wire [4:0] decode_mul_op_o;
  wire [7:0] decode_div_op_o;
  wire [7:0] decode_csr_op_o;
  wire [0:0] decode_fence_op_o;
  wire [1:0] decode_other_op_o;
  wire [0:0] decode_unsupport_op_o;
  wire decode_src1_valid_o;
  wire decode_src2_valid_o;
  wire decode_dest_valid_o;
  Decode inst_Decode
  (
    .clk                  (clk),
    .rst                  (rst),
    .enable               (decode_enable),
    .ready                (decode_ready),
    .inst_i               (decode_inst_i),
    .inst_valid           (decode_inst_valid_i),
    .pc_i                 (decode_pc_i),
    .waddr                (decode_waddr_i),
    .wen                  (decode_wen_i),
    .wdata                (decode_wdata_i),

    .inst_o               (decode_inst_o),
    .src1_valid           (decode_src1_valid_o),
    .src2_valid           (decode_src2_valid_o),
    .dest_valid           (decode_dest_valid_o),
    .pc_o                 (decode_pc_o),
    .src1                 (decode_src1_o),
    .src2                 (decode_src2_o),
    .rs1                  (decode_rs1_o),
    .rs2                  (decode_rs2_o),
    .imm                  (decode_imm_o),
    .dest                 (decode_dest_o),
    .op_valid_o           (decode_op_valid_o),
    .arithmetic_op        (decode_arithmetic_op_o),
    .logic_op             (decode_logic_op_o),
    .branch_op            (decode_branch_op_o),
    .load_op              (decode_load_op_o),
    .store_op             (decode_store_op_o),
    .mul_op               (decode_mul_op_o),
    .div_op               (decode_div_op_o),
    .csr_op               (decode_csr_op_o),
    .fence_op             (decode_fence_op_o),
    .other_op             (decode_other_op_o),
    .unsupport_op         (decode_unsupport_op_o)
  );

  wire [31:0] execute_inst_i;
  wire [63:0] execute_pc_i/*verilator public_flat*/,execute_src1_i,execute_src2_i,execute_imm_i;
  wire [4:0] execute_dest_i,execute_rs1_i,execute_rs2_i;
  wire [6:0] execute_arithmetic_op_i;
  wire [21:0] execute_logic_op_i;
  wire [7:0] execute_branch_op_i;
  wire [7:0] execute_load_op_i;
  wire [3:0] execute_store_op_i;
  wire [4:0] execute_mul_op_i;
  wire [7:0] execute_div_op_i;
  wire [7:0] execute_csr_op_i;
  wire [0:0] execute_fence_op_i;
  wire [1:0] execute_other_op_i;
  wire [0:0] execute_unsupport_op_i;
  wire execute_op_valid_i;

  ID_reg inst_ID_reg
  (
    .clk               (clk),
    .rst               (rst),
    .enable            (decode_enable),
    .flush             (decode_flush),
    .ready             (execute_ready),
    .valid_i           (decode_op_valid_o),
    .inst_i            (decode_inst_o),
    .pc_i              (decode_pc_o),
    .src1_i            (decode_src1_o),
    .src2_i            (decode_src2_o),
    .rs1_i             (decode_rs1_o),
    .rs2_i             (decode_rs2_o),
    .imm_i             (decode_imm_o),
    .dest_i            (decode_dest_o),
    .arithmetic_op_i   (decode_arithmetic_op_o),
    .logic_op_i        (decode_logic_op_o),
    .branch_op_i       (decode_branch_op_o),
    .load_op_i         (decode_load_op_o),
    .store_op_i        (decode_store_op_o),
    .mul_op_i          (decode_mul_op_o),
    .div_op_i          (decode_div_op_o),
    .csr_op_i          (decode_csr_op_o),
    .fence_op_i        (decode_fence_op_o),
    .other_op_i        (decode_other_op_o),
    .unsupport_op_i    (decode_unsupport_op_o),
    
    .inst_o            (execute_inst_i),
    .pc_o              (execute_pc_i),
    .src1_o            (execute_src1_i),
    .src2_o            (execute_src2_i),
    .rs1_o             (execute_rs1_i),
    .rs2_o             (execute_rs2_i),
    .imm_o             (execute_imm_i),
    .dest_o            (execute_dest_i),
    .arithmetic_op_o   (execute_arithmetic_op_i),
    .logic_op_o        (execute_logic_op_i),
    .branch_op_o       (execute_branch_op_i),
    .load_op_o         (execute_load_op_i),
    .store_op_o        (execute_store_op_i),
    .mul_op_o          (execute_mul_op_i),
    .div_op_o          (execute_div_op_i),
    .csr_op_o          (execute_csr_op_i),
    .fence_op_o        (execute_fence_op_i),
    .other_op_o        (execute_other_op_i),
    .unsupport_op_o    (execute_unsupport_op_i),
    .valid_o           (execute_op_valid_i)
  );
  wire [31:0] execute_inst_o;
  wire [63:0] execute_pc_o;
  wire [1:0] execute_other_op_o;
  wire execute_difftest_raise_hard_intr_o;
  wire [63:0] execute_target_pc_o;
  wire execute_target_pc_valid_o;
  wire execute_load_valid_o;
  wire [63:0] execute_load_addr_o;
  wire [3:0] execute_load_bytes_o;
  wire execute_load_sign_o;
  wire execute_store_valid_o;
  wire [63:0] execute_store_addr_o;
  wire [63:0] execute_store_data_o;
  wire [3:0] execute_store_bytes_o;
  wire [4:0] execute_dest_o;
  wire [63:0] execute_dest_data_o;
  wire [63:0] execute_mul_res_o;
  wire [63:0] execute_div_res_o;
  wire execute_dest_valid_o;

  wire [63:0] hazards_src1_o;
  wire [63:0] hazards_src2_o;

  Execute inst_Execute
  (
    .clk           (clk),
    .rst           (rst),
    .enable        (execute_enable),
    .flush         (execute_flush),
    .ready         (execute_ready),
    .div_ready     (div_ready),
    .mul_ready     (mul_ready),
    .inst_i        (execute_inst_i),
    .pc_i          (execute_pc_i),
    .src1          (hazards_src1_o),
    .src2          (hazards_src2_o),
    .imm           (execute_imm_i),
    .dest_i        (execute_dest_i),
    .rs1_i         (execute_rs1_i),
    .rs2_i         (execute_rs2_i),
    .arithmetic_op (execute_arithmetic_op_i),
    .logic_op      (execute_logic_op_i),
    .branch_op     (execute_branch_op_i),
    .load_op       (execute_load_op_i),
    .store_op      (execute_store_op_i),
    .other_op      (execute_other_op_i),
    .mul_op        (execute_mul_op_i),
    .div_op        (execute_div_op_i),
    .fence_op      (execute_fence_op_i),
    .csr_op        (execute_csr_op_i),
    .unsupport_op  (execute_unsupport_op_i),
    .ex_intr       (ex_intr),
    .mtip_clear    (mtip_clear),
    .msip_i        (msip_i),
    .msip_valid_i  (msip_valid_i),
    .msip_o        (msip_o),
    .icache_invalid(icache_invalid),
    .tim_int_req   (tim_int_req),
    .inst_o        (execute_inst_o),
    .pc_o          (execute_pc_o),
    .other_op_o    (execute_other_op_o),
    .difftest_raise_hard_intr(execute_difftest_raise_hard_intr_o),
    .target_pc_o          (execute_target_pc_o),
    .target_pc_valid_o    (execute_target_pc_valid_o),
    .load_valid    (execute_load_valid_o),
    .load_addr     (execute_load_addr_o),
    .load_bytes    (execute_load_bytes_o),
    .load_sign     (execute_load_sign_o),
    .store_valid   (execute_store_valid_o),
    .store_addr    (execute_store_addr_o),
    .store_data    (execute_store_data_o),
    .store_bytes   (execute_store_bytes_o),
    .mul_res       (execute_mul_res_o),
    .div_res       (execute_div_res_o),
    .dest_o        (execute_dest_o),
    .dest_data     (execute_dest_data_o),
    .dest_valid_o  (execute_dest_valid_o)
  );
  wire [31:0] memory_inst_i;
  wire [63:0] memory_pc_i;
  wire [1:0]  memory_other_op_i;
  wire memory_difftest_raise_hard_intr_i;
  wire        memory_load_valid_i;
  wire [63:0] memory_load_addr_i;
  wire [3:0]  memory_load_bytes_i;
  wire        memory_load_sign_i;
  wire        memory_store_valid_i;
  wire [63:0] memory_store_addr_i;
  wire [63:0] memory_store_data_i;
  wire [3:0]  memory_store_bytes_i;
  wire [4:0]  memory_dest_i;
  wire [63:0] memory_dest_data_i;
  wire        memory_dest_valid_i;
  wire [63:0] exe_reg_hazards_data_o;
  wire [4:0]  exe_reg_hazards_dest_o;
  wire        exe_reg_hazards_data_valid_o;
  wire        exe_reg_hazards_dst_valid_o;
  EXE_reg inst_EXE_reg
  (
    .clk               (clk),
    .rst               (rst),
    .flush             (execute_flush),
    .enable            (execute_enable),
    .ready             (memory_ready),
    .inst_i            (execute_inst_o),
    .pc_i              (execute_pc_o),
    .other_op_i        (execute_other_op_o),
    .difftest_raise_hard_intr_i(execute_difftest_raise_hard_intr_o),
    .load_valid_i      (execute_load_valid_o),
    .load_addr_i       (execute_load_addr_o),
    .load_bytes_i      (execute_load_bytes_o),
    .load_sign_i       (execute_load_sign_o),
    .store_valid_i     (execute_store_valid_o),
    .store_addr_i      (execute_store_addr_o),
    .store_data_i      (execute_store_data_o),
    .store_bytes_i     (execute_store_bytes_o),
    .dest_i            (execute_dest_o),
    .dest_data_i       (execute_dest_data_o),
    .dest_valid_i      (execute_dest_valid_o),
    .mul_res_i         (execute_mul_res_o),
    .div_res_i         (execute_div_res_o),
    .inst_o            (memory_inst_i),
    .pc_o              (memory_pc_i),
    .other_op_o        (memory_other_op_i),
    .difftest_raise_hard_intr_o(memory_difftest_raise_hard_intr_i),
    .load_valid_o      (memory_load_valid_i),
    .load_addr_o       (memory_load_addr_i),
    .load_bytes_o      (memory_load_bytes_i),
    .load_sign_o       (memory_load_sign_i),
    .store_valid_o     (memory_store_valid_i),
    .store_addr_o      (memory_store_addr_i),
    .store_data_o      (memory_store_data_i),
    .store_bytes_o     (memory_store_bytes_i),
    .dest_o            (memory_dest_i),
    .dest_data_o       (memory_dest_data_i),
    .dest_valid_o      (memory_dest_valid_i),
    .hazards_data_o(exe_reg_hazards_data_o),
    .hazards_dest_o(exe_reg_hazards_dest_o),
    .hazards_data_valid_o(exe_reg_hazards_data_valid_o),
    .hazards_dst_valid_o(exe_reg_hazards_dst_valid_o)
  );
  assign fetch_branch_pc_i = {64{execute_target_pc_valid_o}}&execute_target_pc_o;
  assign fetch_branch_valid_i = (execute_target_pc_valid_o);

  wire [31:0] memory_inst_o;
  wire [63:0] memory_pc_o;
  wire [1:0]  memory_other_op_o;
  wire        memory_difftest_raise_hard_intr_o;
  wire        memory_difftest_memory_op_o;
  wire [63:0] memory_difftest_memory_addr_o;
  wire        memory_load_sign_o;
  wire        memory_dcache_ren_o;
  wire [63:0] memory_dcache_raddr_o;
  wire [3:0]  memory_dcache_rsize_o;
  wire [63:0] memory_dcache_rdata_i;
  wire [3:0]  memory_dcache_rbytes_i;
  wire        memory_dcache_rdata_valid_i;
  wire        memory_dcache_wen_o;
  wire [63:0] memory_dcache_waddr_o;
  wire [63:0] memory_dcache_wdata_o;
  wire [3:0]  memory_dcache_wsize_o;
  wire [63:0] memory_load_data_o;
  wire        memory_load_valid_o;
  wire [4:0]  memory_dest_o;
  wire [63:0] memory_dest_data_o;
  wire        memory_dest_valid_o;
  wire        memory_dcache_rbusy_i;
  wire        memory_dcache_wbusy_i;
  assign dcache_ren = memory_dcache_ren_o&memory_enable;
  assign dcache_raddr = memory_dcache_raddr_o;
  assign dcache_rsize = memory_dcache_rsize_o;
  assign dcache_wen = memory_dcache_wen_o&memory_enable;
  assign dcache_waddr = memory_dcache_waddr_o;
  assign dcache_wdata = memory_dcache_wdata_o;
  assign dcache_wsize = memory_dcache_wsize_o;
  assign memory_dcache_rdata_i = dcache_rdata;
  assign memory_dcache_rdata_valid_i = dcache_rdata_valid;
  assign memory_dcache_rbusy_i = dcache_rbusy;
  assign memory_dcache_wbusy_i = dcache_wbusy;
  Memory inst_Memory
  (
    .enable             (memory_enable),
    .ready              (memory_ready),
    .dcache_ren         (memory_dcache_ren_o),
    .dcache_raddr       (memory_dcache_raddr_o),
    .dcache_rsize       (memory_dcache_rsize_o),
    .dcache_rdata       (memory_dcache_rdata_i),
    .dcache_rbytes      (memory_dcache_rbytes_i),
    .dcache_rdata_valid (memory_dcache_rdata_valid_i),
    .dcache_rbusy       (memory_dcache_rbusy_i),
    .dcache_wen         (memory_dcache_wen_o),
    .dcache_waddr       (memory_dcache_waddr_o),
    .dcache_wdata       (memory_dcache_wdata_o),
    .dcache_wsize       (memory_dcache_wsize_o),
    .dcache_wbusy       (memory_dcache_wbusy_i),
    .inst_i             (memory_inst_i),
    .pc_i               (memory_pc_i),
    .other_op_i         (memory_other_op_i),
    .difftest_raise_hard_intr_i(memory_difftest_raise_hard_intr_i),
    .load_valid         (memory_load_valid_i),
    .load_addr          (memory_load_addr_i),
    .load_bytes         (memory_load_bytes_i),
    .load_sign          (memory_load_sign_o),
    .store_valid        (memory_store_valid_i),
    .store_addr         (memory_store_addr_i),
    .store_data         (memory_store_data_i),
    .store_bytes        (memory_store_bytes_i),
    .dest_i             (memory_dest_i),
    .dest_data_i        (memory_dest_data_i),
    .dest_valid_i       (memory_dest_valid_i),
    .inst_o             (memory_inst_o),
    .pc_o               (memory_pc_o),
    .other_op_o         (memory_other_op_o),
    .difftest_raise_hard_intr_o(memory_difftest_raise_hard_intr_o),
    .difftest_memory_op_o(memory_difftest_memory_op_o),
    .difftest_memory_addr_o(memory_difftest_memory_addr_o),

    .load_data_o        (memory_load_data_o),
    .load_valid_o       (memory_load_valid_o),
    .dest_data_o        (memory_dest_data_o),
    .dest_o             (memory_dest_o),
    .dest_valid_o       (memory_dest_valid_o)
  );
  wire [31:0] writeback_inst_i;
  wire [63:0] writeback_pc_i;
  wire [1:0]  writeback_other_op_i;
  wire        writeback_difftest_raise_hard_intr_i;
  wire        writeback_difftest_memory_op_i;
  wire [63:0] writeback_difftest_memory_addr_i;
  wire [4:0]  writeback_dest_i;
  wire [63:0] writeback_dest_data_i;
  wire        writeback_dest_valid_i;
  wire [63:0] writeback_load_data_i;
  wire        writeback_load_valid_i;
  wire [63:0] mem_reg_hazards_data_o;
  wire [4:0]  mem_reg_hazards_dest_o;
  wire        mem_reg_hazards_data_valid_o;
  MEM_reg inst_MEM_reg
  (
    .clk          (clk),
    .rst          (rst),
    .flush        (memory_flush),
    .enable       (memory_enable),
    .ready        (writeback_ready),
    .inst_i       (memory_inst_o),
    .pc_i         (memory_pc_o),
    .other_op_i   (memory_other_op_o),
    .difftest_raise_hard_intr_i(memory_difftest_raise_hard_intr_o),
    .difftest_memory_op_i(memory_difftest_memory_op_o),
    .difftest_memory_addr_i(memory_difftest_memory_addr_o),
    .dest_data_i  (memory_dest_data_o),
    .dest_i       (memory_dest_o),
    .dest_valid_i (memory_dest_valid_o),
    .load_data_i  (memory_load_data_o),
    .load_valid_i (memory_load_valid_o),
    .load_sign_i  (memory_load_sign_i),
    .load_bytes_i (memory_dcache_rsize_o),
    .load_data_valid_i(dcache_rdata_valid),
    .load_bytes_o (memory_dcache_rbytes_i),
    .load_sign_o  (memory_load_sign_o),
    .inst_o       (writeback_inst_i),
    .pc_o         (writeback_pc_i),
    .other_op_o   (writeback_other_op_i),
    .difftest_raise_hard_intr_o(writeback_difftest_raise_hard_intr_i),
    .difftest_memory_op_o(writeback_difftest_memory_op_i),
    .difftest_memory_addr_o(writeback_difftest_memory_addr_i),
    .dest_data_o  (writeback_dest_data_i),
    .dest_o       (writeback_dest_i),
    .dest_valid_o (writeback_dest_valid_i),
    .load_data_o  (writeback_load_data_i),
    .load_valid_o (writeback_load_valid_i),
    .hazards_data_o(mem_reg_hazards_data_o),
    .hazards_dest_o(mem_reg_hazards_dest_o),
    .hazards_data_valid_o(mem_reg_hazards_data_valid_o)
  );
  wire [31:0] writeback_inst_o;
  wire [63:0] writeback_pc_o;
  wire [1:0]  writeback_other_op_o;
  wire writeback_difftest_raise_hard_intr_o;
  wire writeback_difftest_memory_op_o;
  wire [63:0] writeback_difftest_memory_addr_o;
  wire [4:0] writeback_waddr_o;
  wire writeback_wen_o;
  wire [63:0] writeback_wdata_o;
  assign decode_waddr_i = writeback_waddr_o;
  assign decode_wen_i = writeback_wen_o&writeback_enable;
  assign decode_wdata_i = writeback_wdata_o;
  Writeback inst_Writeback
  (
    .enable       (writeback_enable),
    .ready        (writeback_ready),
    .inst_i       (writeback_inst_i),
    .pc_i         (writeback_pc_i),
    .other_op_i   (writeback_other_op_i),
    .difftest_raise_hard_intr_i(writeback_difftest_raise_hard_intr_i),
    .difftest_memory_op_i(writeback_difftest_memory_op_i),
    .difftest_memory_addr_i(writeback_difftest_memory_addr_i),
    .dest_data_i  (writeback_dest_data_i),
    .dest_i       (writeback_dest_i),
    .dest_valid_i (writeback_dest_valid_i),
    .load_data_i  (writeback_load_data_i),
    .load_valid_i (writeback_load_valid_i),
    .inst_o       (writeback_inst_o),
    .pc_o         (writeback_pc_o),
    .other_op_o   (writeback_other_op_o),
    .difftest_raise_hard_intr_o(writeback_difftest_raise_hard_intr_o),
    .difftest_memory_op_o(writeback_difftest_memory_op_o),
    .difftest_memory_addr_o(writeback_difftest_memory_addr_o),
    .waddr        (writeback_waddr_o),
    .wen          (writeback_wen_o),
    .wdata        (writeback_wdata_o)
  );

  wire [4:0] Hazards_enable,Hazards_flush,Hazards_ready,Hazards_busy;
  
  assign {writeback_enable,memory_enable,execute_enable,decode_enable,fetch_enable} = Hazards_enable;
  assign Hazards_ready = {writeback_ready,memory_ready,execute_ready,decode_ready,fetch_ready};
  assign Hazards_busy = {writeback_busy,memory_busy,execute_busy,decode_busy,fetch_busy};
  assign {writeback_flush,memory_flush,execute_flush,decode_flush,fetch_flush} = Hazards_flush;

  wire [4:0] Hazards_data_valid;
  Hazards_ctrl inst_Hazards_ctrl
  (
    .clk          (clk),
    .rst          (rst),
    .enable       (Hazards_enable),
    .flush        (Hazards_flush),
    .ready        (Hazards_ready),
    .busy         (Hazards_busy),
    .data_valid   (Hazards_data_valid),
    .id_rs1       (decode_rs1_o),
    .id_rs2       (decode_rs2_o),
    .id_dst       (decode_dest_o),
    .exe_dst      (execute_dest_o),
    .mem_dst      (memory_dest_o),
    .wb_dst       (writeback_waddr_o),
    .branch_miss  (execute_target_pc_valid_o),
    .icache_busy  (icache_rbusy),
    .dcache_busy  (dcache_rbusy|dcache_wbusy),
    .id_rs1_valid (decode_src1_valid_o),
    .id_rs2_valid (decode_src2_valid_o),
    .id_dst_valid (decode_dest_valid_o),

      /* These data come from pipeline regs. */
    .id_rs1_r(execute_rs1_i),
    .id_rs2_r(execute_rs2_i),
    .id_src1_r(execute_src1_i),
    .id_src2_r(execute_src2_i),

    .exe_dst_valid_r(exe_reg_hazards_dst_valid_o),
    .exe_data_valid_r(exe_reg_hazards_data_valid_o),
    .exe_dst_r(exe_reg_hazards_dest_o),
    .exe_data_r(exe_reg_hazards_data_o),
    .mem_data_valid_r(mem_reg_hazards_data_valid_o),
    .mem_dst_r(mem_reg_hazards_dest_o),
    .mem_data_r(mem_reg_hazards_data_o),
    /* This data comes from writenack unit. */
    .wb_en_i(writeback_wen_o),
    .wb_dst_i(writeback_waddr_o),
    .wb_data_i(writeback_wdata_o),
    /* These data go to execute unit. */
    .id_src1_o(hazards_src1_o),
    .id_src2_o(hazards_src2_o)
  );

  difftest inst_difftest
  (
    .clk            (clk),
    .rst            (rst),
    .data_valid     (Hazards_data_valid),
    .writeback_enable(writeback_enable),
    .writeback_inst (writeback_inst_o),
    .writeback_difftest_raise_hard_intr(writeback_difftest_raise_hard_intr_o),
    .writeback_other_op(writeback_other_op_o),
    .difftest_memory_op_i(writeback_difftest_memory_op_o),
    .difftest_memory_addr_i(writeback_difftest_memory_addr_o),
    .fetch_pc       (fetch_pc_o),
    .decode_pc      (decode_pc_o),
    .execute_pc     (execute_pc_o),
    .memory_pc      (memory_pc_o),
    .writeback_pc   (writeback_pc_o)
  );


endmodule
